Electronic Design

Use Hybrid PMOS-NMOS Active Loads To Cut Substrate Noise In Differential Amplifiers

PMOS transistors are less vulnerable to substrate noise since they’re placed in separate wells; designers implement guard rings to attenuate the substrate noise propagation. However, substrate noise ...
Electronic Design

Dirt Cheap ASIC Design for Dummies (Part 3): NMOS, PMOS Silicon Design Using a Web Browser

Quickly learn what the difference is between PMOS and NMOS transistors in their structure and operation, and how CMOS works with the two in combination. Siliwiz, a free, browser-based, ASIC layout ...
sciencex

Towards a process flow for monolithic CFET transistor architectures

—The development of a process flow capable of demonstrating functionality of a monolithic complementary FET (CFET) transistor architecture is complex due to the need to vertically separate nMOS and ...
Electronics Weekly

X-Fab adds 375V nmos and pmos super-junction transistors to BCD chip process

X-Fab Silicon Foundries has added 375V power transistors to the devices available from its 180nm deep trench isolation BCD-on-SoI platform chip fab. The second generation of its XT018 super-junction ...
The Engineer

On Building Physically Accurate Analogue Switch Macromodels

I was testing a circuit and found many discrepancies from the paper design I used to create it. The dynamics of the circuit were a bit unexpected, andthe noise level was much larger than required. I ...